Electronic components such as semiconductor elements are mounted on wiring substrates. A wiring substrate that undergoes a build-up process stacks wiring layers and insulation layers on the upper and lower surfaces of a wiring substrate to increase the density of wiring patterns. Japanese Laid-Open Patent Publication Nos. 2003-023252 and 05-144811 each describe examples of such a wiring substrate.
In such type of a wiring substrate, a roughening process is performed on each wiring layer to improve adhesion with the corresponding insulation layer that covers the wiring layer.
The roughening process changes the wiring layers in shape more greatly as the wiring layers become finer. Thus, the desired shapes of the fine wiring layers may not be maintained when performing the roughening process. When omitting the roughening process to avoid such a situation, the adhesion will decrease between the wiring layer and the insulation layer covering the wiring layer. In such a case, delamination is apt to occur at the interface of the wiring layer and the insulation layer. The occurrence of such a delamination may lead to corrosion of the wiring layer when conducting a reliability test such as the biased Highly-Accelerated Temperature and Humidity Stress Test (biased HAST).